Static random-access memory (SRAM) is a common type of semiconductor memory that uses flip-flop circuitry to store bits of binary data. Unlike dynamic random-access memory (DRAM), SRAM, though volatile, does not require periodic refreshing to ensure data is not distorted. SRAM is traditionally composed of arrays of SRAM bit cells. Each SRAM bit cell, typically composed of six or more transistors, stores a single bit of data that may be accessed by a pair of complementary bit lines. As memory technology has continued to advance, problems have arisen in maintaining SRAM bit cells as transistor memory technology produces smaller sizes with lower power structures. Specifically, the minimum voltage required for reliable operation of a SRAM cell is not scaling as fast as the operating supporting logic and write assist circuits. As a result, current SRAM cells are using dual power supplies, with one power supply, such as VDD, used to power the SRAM peripheral circuitry and a second power supply operating at a higher voltage, VCS, to power the memory array and bit cells. As a result of the two different voltages and power sources, the SRAM cell must be able to reconcile the two voltages. One solution to this issue is the use of voltage level shifting or level translation circuitry. A disadvantage associated with voltage level shifting and level translation circuitry is the need for additional space on a product to house these components, and additional power consumption to drive shifts between voltage levels.